Senior Logic Design Engineer

Introduction

At IBM Infrastructure & Technology, we engineer and manage the systems that power our world. Our work encompasses high-resilience mainframes, hybrid cloud platforms, networking, automation, and site reliability. Our teams guarantee the performance, security, and scalability that industries and clients rely on daily. Engaging with Infrastructure & Technology means addressing intricate challenges through curiosity and teamwork. You will collaborate with a variety of technologies and colleagues globally to provide resilient, future-oriented solutions fostering innovation. IBM offers continuous learning, career advancement, and a nurturing culture, providing you with the opportunity to develop expertise and influence the infrastructure that propels progress.

Your Role And Responsibilities

• Work alongside micro architects and designers to propose and showcase core CPU micro architectural features aimed at enhancing performance per area/power on specified workloads.
• Partner with the Silicon Bringup team and Software team to validate and troubleshoot microarchitecture and its performance.
• Exhibit strong communication skills and the ability to finalize micro architectural proposals within the Core and Cache team, engaging with technical stakeholders across Chip/System through presentations and documentation.
• Demonstrate strong collaborative and interpersonal abilities, with a proven track record of mentoring new design team members.
  
  

Preferred Education

Master's Degree

Required Technical And Professional Expertise

• 8-15 years of experience in high-performance microprocessor architecture, micro architecture, or computer architecture.
• Extensive knowledge of Processor Instruction set architecture (e.g., ARM, X86, Power).
• In-depth understanding and experience with CPU microarchitecture and architecture, including: Fetch, Decode, Load-Store, L1, L2 caches, Prefetch, and Coherency.
• Familiarity with Memory Design, Memory Ordering Rules, Load-Store, Pipeline optimization, and PPA optimization is preferred.
• Robust RTL design expertise coupled with hands-on experience in Processor/ASIC design flow: design, verification, physical design synthesis, ECO, and bring up.
  
  

Preferred Technical And Professional Experience

• Advanced Static Timing: A comprehensive understanding of static timing and its application in chip logic development can be beneficial for driving business outcomes.
• Front-end Processing Expertise: Knowledge of front-end processing and its significance in chip logic development can be instrumental in shaping cognitive systems logic design's future.
• Post-Si debug: Experience with Post-Si debugging is desirable.
• Performance & Power Analysis: Experience in analyzing Performance & Power Tools data and developing features to address PPA concerns is advantageous.