Physical Design Engineer

Skills/Experience:

• Hands-on experience in complex SOC/sub-systems implementation using Innovus & Fusion Compiler.
• Proficient in top-down floorplan and Power Grid methodologies.
• Experience in signoff convergence, block-level Timing Signoff, ECO generation, and Power signoff.
• Successful track records of taping out complex IPs & SoCs at 16/10/7/5 nm Power user of Cadence implementation tools, such as Genus, Innovus, Quantus, Tempus, PVS, Voltus.
• Automation and programming-minded, coding experience in Tcl/Tk/Perl.