Senior Logic Design Engineer

Introduction

At IBM Infrastructure & Technology, we build and operate the systems that keep the world moving. Our work spans high-resiliency mainframes and hybrid cloud environments, as well as networking, automation, and site reliability. We help ensure the performance, security, and scalability that clients and industries rely on every day. In Infrastructure & Technology, you’ll take on intricate problems through curiosity and teamwork. You’ll collaborate with experienced professionals and diverse technologies worldwide to deliver resilient, future-ready solutions that support innovation. With ongoing learning, career advancement, and a culture built on support, IBM enables you to develop expertise and help shape the infrastructure driving progress.

Your Role And Responsibilities

• Own the microarchitecture, design, and development of the Instruction Fetch Unit for a high-performance Processor CPU in IBM Systems.
• Perform micro-architecting and design of Instruction Fetch, Instruction Decode, Branch Predictors, and the Instruction Queue for a high performance processor CPU.
• Develop product features and present the proposed architecture during High-level design discussions.
• Assess and estimate the overall effort required to develop the feature.
• Estimate silicon area and wire usage for the feature.
• Develop microarchitecture and RTL design; collaborate with other Core units and partner groups including Verification, DFT, Physical design, Timing, FW, and SW teams to deliver the feature.
• Provide signoff for the pre-silicon design that meets all functional, area, and timing objectives.
• Support post-silicon lab bring-up and hardware validation.
• Lead a team of engineers; guide and mentor team members; and represent as Logic Design Lead in global forums.
  
  

Preferred Education

Master's Degree

Required Technical And Professional Expertise

• 8 to 15 or more years of demonstrated experience in architecting and designing Instruction Fetch, Decode and Branch Predictor unit of CPU
• Hands of experience of implementing Issue Queues, Arrays, Caches, Reordering Buffer and Pipeline flush/exception handling
• Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA
• Experience with high frequency, instruction pipeline designs
• At least 1 generation of Processor Core silicon bring up experience
• In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs)
• Proficiency of RTL design with Verilog or VHDL
  
  

Preferred Technical And Professional Experience

• Knowledge of Out-of-Order, Memory and Execution units
• Knowledge of verification principles and coverage
• High-level knowledge of Linux operating system
• Knowledge of one object oriented language and scripting language
• Understanding of Agile development processes
• Experience with DevOps design methodologies and tools
• Advanced Static Timing: Deep understanding of static timing and its application in chip logic development can be advantageous in driving business results.
• Front-end Processing Expertise: Familiarity with front-end processing and its role in chip logic development can be valuable in shaping the future of cognitive systems logic design.
• Post-Si debug: Familiarity with Post-Si debugs is preferable.
• Performance & Power Analysis: Familiarity with analysing Performance & Power Tools data and coming up with features solving PPA issues.