Chip Design Integration Engineer

Introduction

At IBM Infrastructure & Technology, we engineer and run the systems that keep the world moving. Our work spans high-resiliency mainframes and hybrid cloud platforms, along with networking, automation, and site reliability. We help ensure the performance, security, and scalability that clients and industries rely on every day. If you join Infrastructure & Technology, you’ll tackle complex problems with curiosity and teamwork. You’ll collaborate with a global community and work with diverse technologies to deliver resilient, future-ready solutions that support innovation. With ongoing learning, career advancement, and a culture built on support, IBM helps you grow your expertise and contribute to the infrastructure driving progress.

Your Role And Responsibilities

As a Hardware Developer for Cognitive Systems, you will design, develop, test, and deliver offerings for Power & Z using state-of-the-art technologies. You will define the physical design and establish the chip footprint layout, ensuring that all design constraints are satisfied.

Your Primary Responsibilities Will Include

• Design and Develop Offerings: Design, develop, test, and deliver offerings for Power & Z using the latest technologies, defining the physical design and laying out the chip footprint.
• Perform Chip Integration: Interconnect all circuits, arrays, random logic, and I/O on the chip according to a defined set of ground rules for the selected silicon technology.
• Verify Design Constraints: Run a series of checks (software runs) to confirm that all design constraints are met, using toolsets such as Cadence or other proprietary tools.
• Manage Chip Footprint: Define the physical design and lay out the chip footprint, ensuring efficient use of space and alignment with design requirements.
  
  

Preferred Education

Master's Degree

Required Technical And Professional Expertise

• Chip Design Development: Experience designing, developing, testing, and delivering offerings for Power & Z using the latest technologies, including defining physical designs and laying out chip footprints.
• Chip Integration Engineering: Experience interconnecting circuits, arrays, random logic, and I/O on chips to satisfy ground rules for the selected silicon technologies.
• Design Constraint Verification: Experience performing software runs to verify design constraints, using toolsets such as Cadence or other proprietary tools.
• Silicon Technology Application: Experience applying silicon technology knowledge to enable effective chip design and integration.
• Physical Design Optimization: Experience optimizing physical designs to meet space and performance requirements.
  
  

Preferred Technical And Professional Experience

• Familiarity with Proprietary Tools: Experience with Cadence or other proprietary tools for running software checks to verify design constraints is beneficial.
• Knowledge of Silicon Technologies: Understanding of various silicon technologies and how to apply them in chip design and integration is advantageous.
• Physical Design Principles: Familiarity with physical design optimization principles to achieve space and performance requirements is desirable.