Logic Design Engineer

Introduction

At IBM Infrastructure & Technology, we build and run the systems that keep the world moving. Our work spans high-resiliency mainframes, hybrid cloud platforms, networking, automation, and site reliability. We help ensure the performance, security, and scalability that clients and industries rely on daily. In Infrastructure & Technology, you tackle challenging problems through curiosity and collaboration, partnering with a global team and working across a wide range of technologies. You’ll contribute to resilient, future-ready solutions that support innovation. With ongoing learning, career advancement, and a supportive culture, IBM enables you to grow your expertise and help shape the infrastructure that drives progress.

Your Role And Responsibilities

Your primary responsibilities will include:

• Define and document microarchitecture for assigned functional blocks, including pipeline structure, data-path organisation, and control logic.
• Write clean, synthesisable RTL in VHDL or SystemVerilog, following team coding standards and meeting lint/CDC/RDC cleanliness targets.
• Partner with architects to assess design options and clearly communicate area, power, and frequency trade-offs.
• Lead design debug across simulation, emulation, and post-silicon environments; create debug approaches and resolve root-cause RTL or logic issues efficiently.
• Own timing closure for assigned blocks: perform critical-path analysis, apply SDC constraints, support ECO strategies, and collaborate with physical design to achieve frequency targets.
• Evaluate and approve verification plans, ensuring functional coverage objectives match the microarchitectural intent.
• Participate in design reviews and contribute to cross-project lessons-learned to enhance team-wide processes.
• Mentor junior engineers on RTL quality, debug methodology, and core timing principles.
  
  

Preferred Education

Master's Degree

Required Technical And Professional Expertise

• 5–10 years in digital ASIC or processor logic design, Microarchitecture definition and specification authoring.
• RTL coding in SystemVerilog and/or VHDL
• Static timing analysis (STA) and SDC constraint authoring
• Timing closure — path analysis, ECOs, hold/setup fixing
• Design debug: simulation, waveform analysis, emulation
• Logic synthesis (Synopsys DC, Cadence Genus, or equivalent)
• Lint, CDC, and RDC analysis tools (SpyGlass or equivalent)
• Familiarity with formal verification flows
• Cross-functional collaboration with physical design and DFT
  
  

Preferred Technical And Professional Experience

• Experience in high-performance processor, memory subsystem, or high-speed interconnect design (e.g. PCIe, NVLink, OpenCAPI).
• Exposure to power analysis and low-power design techniques (clock gating, power domains, UPF/CPF).
• Post-silicon bring-up and debug experience including lab instrumentation and JTAG-based debug flows.
• Familiarity with emulation platforms (Palladium, Zebu) for pre-silicon debug at speed.
• Proven ability to drive an RTL block from specification through tapeout on a commercial product.