Timing and Synthesis Engineer, Senior

General Summary

• Qualcomm is a tech innovator focusing on next-gen products.
• Role involves planning, designing, optimizing, verifying, and testing various electronic systems including digital, analog, RF, optical, FPGA, DSP, and mechanical systems.
• Collaborate with cross-functional teams to meet performance and quality requirements.
• Support multiple SoC design teams in logic synthesis, power-aware synthesis (UPF), quality of results (QoR) optimization, and netlist signoff flows.
• Troubleshoot and debug synthesis/implementation issues.
• Develop and maintain third-party tool integrations and product enhancements.
• Evaluate new tools and refine methodologies for power, performance, and area (PPA) optimization.

Minimum Qualifications

• Education:
• Bachelor's degree + 2+ years hardware engineering or related experience;
• OR
• Master's degree + 1+ year experience;
• OR
• PhD in relevant field (CS, Electrical/Electronics Engineering, etc.)
• Experience:
• 3 to 5 years experience in RTL design, UPF (Unified Power Format), physical-aware synthesis for advanced process nodes.
• Logic equivalence checking (LEC), scripting, and netlist timing signoff expertise.