STA/Timing Methodology Sr Staff Engineer

Key requirements:

Thorough knowledge of the ASIC design cycle and timing closure flow and methodology.

10 + years of proficiency in timing constraints and timing closure. Expertise in STA tools (any of Primetime, Tempus, Tweaker) and flow.

Strong understanding of advanced STA concepts and challenges in advanced nodes

Proficiency scripting languages (TCL, Perl, Python).

Strong background in PNR and Extraction domain.

Experience of constraints development tool (like spyglass) will be added advantage.

Leadership qualities to lead (technically) and manage the STA CAD team

Qualification:

BE/BTech + 12 years of experience, or ME/MTech + 10 years of experience

Minimum Qualifications:

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.

OR

Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.

OR

PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.