QU

Staff STA Engineer

Noida ₹8-12 LPA Posted 26 May 2025

FULL TIME

low power design

Timing Closure

Static Timing Analysis

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
8 to 12 years of experience in static timing analysis, constraints and other physical implementation aspects.
Solid understanding industry standard tools PT, Tempus, GENUS, Innovus, ICC etc.
Solid grip on STA fixing aspects to solve extreme critical timing bottleneck paths.
Should have experienced about preparing complex ECOs for timing convergence [ across huge set of corners] through Tweaker / Tempus / Physical PT ECOs.
Should be aware about the tricks for minimizing power.
Experience in deep submicron process technology nodes is strongly preferred.
Knowledge of high performance and low power implementation methods is preferred.
Willing to push PPA to the best possible extent.
Strong fundamentals.
Expertise in Perl, TCL language