STA/ Synthesis - Engineer

• Synthesis, Static Timing Analysis and LEC of SoC/Cores
• Full chip and block level timing closure, IO budgeting for blocks
• Logical equivalence check between RTL to Netlist and Netlist to Netlist
• Knowledge of low-power techniques including clock gating, power gating and MV designs
• ECO timing flow
• Proficient in scripting languages (TCL and Perl).

Minimum Qualifications:

• Bachelors degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
• OR
• Masters degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
• OR
• PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.