STA Engineer

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
• OR
• Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
• OR
• PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.
• 3 to 5 years of experience in static timing analysis, constraints and other physical implementation aspects.
• Solid understanding industry standard tools PT, Tempus, And should be familliar to PNR tools like Innovus/FC
• Solid grip on STA fixing aspects to solve extreme critical timing and clock path analysis
• Should have experienced about preparing complex ECOs for timing convergence [ across huge set of corners] through Tweaker / Tempus / Physical PT ECOs and manual ECOs as well.
• Experience in deep submicron process technology nodes is strongly preferred - Below 10nm
• Knowledge of high performance and low power interface timing is added benefit.
• Strong fundamentals on basic VLSI design concepts, synchronous design timing checks, understanding of constraints
• Good experience with in Unix, TCL, PT-TCL, Tempus-TCL scripting
• Familiarity with Python background is added bonus