The environment must support identifying verification environment requirements from various sources like specifications, design functionality, and interfaces.
It needs to generate verification test plans, verification environment documentation, and test environment usage documentation.
The environment should allow you to define, develop, and verify complex UVM verification environments.
It must enable evaluating and exercising various aspects of the development flow, including Verilog/SystemVerilog development, functional simulation, constraint development, test planning, behavioral modeling, and verification coverage metrics (functional coverage and code coverage).
The environment should facilitate collaboration with architects, designers, and VIP teams.
It needs to help identify design problems, possible corrective actions, and inconsistencies in documented functionality.
The environment should support improving methodologies and execution efficiency.
It must adhere to quality standards and good test and verification practices.
The environment should assist leads in mentoring junior engineers and debugging complex problems.
It needs to support reproduction and analysis of customer issues.
The environment's infrastructure should allow for multitasking between different activities.
It requires knowledge of Verilog, VHDL, and/or SystemVerilog.
Proficiency with scripting languages (BASH/TCSH/PERL/PYTHON/TCL) is a plus.
An understanding of UVM verification methodology is essential.

Sr.Staff ASIC Verification Engineer

Job Description

Required Skills