Sr. Silicon Design Engineer

The Role

We are looking for an adaptive, self-motivated design verification engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The Verification Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.

The Person

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

Key Responsibilities:

• Develop, maintain, and enhance test environment/regression, and testbench.
• Work on IP/block testing and debugging.
• Work on functional & code coverage, and performance/power testing.
• Support SoC integration and bridge the gap between IP and SoC.
• Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified.
• Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases.
• Estimate the time required to write the new feature tests and any required changes to the test environment.
• Build the directed and random verification tests.
• Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues.
• Review functional and code coverage metrics, modify or add tests or constrain random tests to meet the coverage requirements.

Preferred Experience:

• ASIC design verification experience with 3 to 6 years.
• Hands-on experience in developing complex UVC.
• Good debugging skill and good knowledge of verification tool and methodology.
• Hands-on experience with coverage planning, coding, and coverage closure.
• Should have worked on developing testplan at module level/IP level/Chip-level project.
• Proficient in IP level ASIC verification.
• Proficient in debugging firmware and RTL code using simulation tools.
• Proficient in using UVM testbenches and working in Linux and Windows environments.
• Experienced with Verilog, System Verilog, C, and C++.
• Developing UVM based verification frameworks and testbenches, processes and flows.
• Strong background in the C++ language, preferably on Linux with exposure to Windows platform.
• Good understanding and hands-on experience in the UVM concepts and SystemVerilog language.
• Scripting language experience: Perl, Ruby, Makefile, shell preferred.

Academic Credentials:

• Bachelor's or Master's degree in ECE, Electrical engineering degree or Master's degree preferred with emphasis in Electrical/Electronics Engineering. Preferred VLSI major in post-graduation.