AM

Sr. Silicon Design Engineer

AMD
Bangalore3-7 LPA Posted 14 Apr 2025
FULL TIME
Ips
Soc
Designing

Job Description

THE ROLE: 

As a member of the NBIO IP Physical aware group, you will help bring to life cutting-edge designs. As a member of the Physical aware person, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve best quality and PPA for complex IPs

 

 

 

THE PERSON:

A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills.

 

KEY RESPONSIBLITIES:

  • Synthesis of Complex IPs, constraint development.
  • Physical aware activity Floorplan, Placement, clock tree synthesis routing.
  • Develop feedback to RTL team for physically driven micro architecture changes, Manage data for shared design across multiple projects.
  • coordination with multiple SOC for complex IPs
  • Lead team for junior team member, guide them and help technical areas.
  •  

 

PREFERRED EXPERIENCE:

  • Understanding of Physical design and synthesis design cycle.
  • 8+ experience in physical design and synthesis domain

 

ACADEMIC CREDENTIALS:

  • Bachelors or Masters degree in computer engineering/Electrical Engineering/Electronics Engineering

Required Skills

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