CA

Sr Principal Verification Engineer

Cadence
Noida5-9 LPA Posted 5 Jun 2026
FULL TIME
Machine Learning
Ml
Verilog
Uvm
formal verification
+3 more

Job Description

Key Responsibilities

AI-Driven Verification Innovation

  • Apply machine learning techniques to enhance pre-silicon functional verification workflows (formal verification and UVM-based methodologies)
  • Develop agentic AI systems using LLMs to accelerate verification processes
  • Utilize AI-powered EDA tools to improve efficiency and accuracy in design and verification lifecycles

Functional Verification Leadership

  • Lead development and execution of pre-silicon verification strategies
  • Work with formal verification and/or UVM-based verification environments
  • Debug complex verification failures using waveform and simulation analysis tools

Tool & Methodology Expertise

  • Work with industry-standard EDA tools such as Jasper, Xcelium, and IMC
  • Ensure correctness and completeness of verification flows across multiple design stages

AI/ML Collaboration & Development

  • Collaborate with ML engineers building large-scale LLM and AI systems
  • Contribute to RAG, reinforcement learning, and agentic framework-based solutions for verification
  • Validate AI-generated outputs for correctness, efficiency, and quality

Customer & Cross-Team Collaboration

  • Engage with customers to understand verification requirements and challenges
  • Work closely with software engineering and AI teams to deliver production-grade solutions
  • Translate customer needs into scalable verification methodologies

Continuous Learning & Innovation

  • Stay updated on advancements in AI-powered hardware verification

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