CACadence Design Systems
Sr Principal RTL Design Engineer
Bangalore ₹4-10 LPA Posted 29 May 2025
FULL TIME
Coding
Usb
Sata
Pcie
Ethernet
+5 more
Job Description
- 12+ years of experience in ASIC design
- Proficient in Verilog coding, RTL design and complex control path and data path designs
- Knowledge of any of the interface Protocols like UCIe, PCIe, USB, MIPI(DPHY), HDMI/Display, Ethernet, SATA
- Knowledge of RTL checks ex- LINT, SDC, CDC Familiar with synthesis flow, LEC and timing constraints
- Experience in writing Verilog testbench and running simulations.