CACadence Design Systems
Sr Principal Product Validation Engineer
Noida ₹8-13 LPA Posted 29 May 2025
FULL TIME
C++
Verilog
Simulation
Vhdl
Job Description
- The person should be an Electrical, Electronics or Computer Science Engineer with very good understanding of HDLs (Verilog and/ or VHDL).
- Prior experience in simulation/emulation using these languages. He/ she should have a good working knowledge of EDA tools (Cadence/ Others) with focus towards debugging design/ verification problems using these tools.
- Experience in process automation with scripting.
- Experience with SystemVerilog, C++, UVM.
- Experience with Functional Verification of complex digital systems, e.g. SoC Verification, with a Hardware Verification Language (HVL) like SystemVerilog.
- Experience designing and implementing complex functional verification environments is required.
- Knowledge of protocols like PCIe, USB3/4, DP an added advantage.