Sr Principal Design Engineer

Key Responsibilities

• Design, develop, and maintain UVM-based verification environments for complex IP blocks.
• Define and implement verification architecture, testbench strategies, and reusable components.
• Develop comprehensive test plans ensuring functional coverage and design completeness.
• Execute debugging of complex IP designs and perform root-cause analysis of failures.
• Drive simulation, regression, and coverage closure activities for IP verification.
• Review and enhance verification test plans to ensure quality and completeness.
• Collaborate with RTL design, architecture, and system teams for IP integration and validation.
• Mentor junior engineers and promote verification best practices across the team.
• Contribute to verification methodology improvements and process optimization.
• Ensure high-quality delivery of IP verification for advanced SoC applications.