Sr Principal Design Engineer

Key Responsibilities

• Architect, develop, and maintain reusable UVM-based verification environments for IP-level validation
• Lead the development of testbench infrastructure, simulation setups, and regression frameworks
• Review, define, and enhance verification test plans to ensure completeness, correctness, and optimal coverage
• Perform deep debugging of complex IP designs and efficiently resolve functional and integration issues
• Drive verification strategy improvements, including methodology enhancements and best practices adoption
• Mentor and guide junior and mid-level engineers in verification techniques, debugging, and UVM methodology
• Collaborate closely with RTL design, architecture, and system teams to ensure seamless IP integration
• Contribute to verification closure by ensuring high-quality deliverables and first-pass silicon success
• Support verification planning and execution for IP integration into advanced SoC systems
• Continuously improve simulation efficiency, coverage metrics, and regression strategies