What You ll Be Doing:Manage and lead a team of 7-8 SoC/Subsystem RTL Design Engineers for various customer engagements.
Work with Synopsys customers to understand their needs and define RTL Signoff and design scope and activities.
Lead the team to perform various RTL Design and Signoff activities for SoC Subsystems such as SoC u-Architecture and Integration, RTL Design (Verilog/SystemVerilog), Lint, CDC, RDC, Synthesis, Constraints Development.
Assist and mentor the team in day-to-day activities and grow the capabilities of the RTL Design team for future assignments.
Review various results and reports to provide continuous feedback to the team and improve the quality of deliverables.
Report status to management and provide suggestions to resolve any issues that may impact execution.
Understand the complexity and requirements of RTL Quality Signoff and propose resource requirements to complete the activities.
Work with peers to improve methodology and improve execution efficiency.
Collaborate with other Synopsys teams including BU AEs and Sales to develop, broaden and deploy Tools.
Train the team in design concepts and root-cause analysis.

The Impact You Will Have:Drive the successful delivery of SoC Subsystems by leading a skilled team of RTL Design Engineers.
Enhance the quality and efficiency of RTL Design and Signoff processes through continuous feedback and methodology improvements.
Ensure customer satisfaction by understanding their needs and delivering high-quality solutions.
Contribute to the growth and development of the RTL Design team, expanding their capabilities for future projects.
Support Synopsys reputation as a leader in chip design and verification through successful project execution.
Foster collaboration and innovation within the team and across different Synopsys departments.

What You ll Need: B.E/B. Tech/M.E/M. Tech in electronics with a minimum of 12+ years experience in SoC RTL Design.
Technical expertise in various aspects of RTL Design and Signoff: LINT, CDC, RDC.
Technical expertise on setting up flows and methodologies for quick deployment of RTL Signoff tools.
Technical expertise in debugging and diagnosing violations and errors.
Technical expertise in developing timing constraints and running preliminary synthesis for timing constraints check and area estimation.
Ability to lead and manage a team to perform RTL Signoff on complex SoC/Subsystem.
Experience with planning and managing various activities related to RTL Signoff and Design.
Strong understanding of design concepts, ASIC flows, and stakeholders.
Good communication skills.

SOC RTL Engineering - Senior Manager