QU

SoC Physical Design Engineer

Qualcomm
Bangalore3-8 LPA Posted 26 May 2025
FULL TIME
Sta
Physical Design
low power design
PNR

Job Description

  • Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
  • OR
  • Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
  • OR
  • PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
  • Bachelor or Master degree from a top-tier institute.
  • 6-11 years of experience in physical design from product-based companies.

Experience:

  • Proven experience in managing complex subsystems and small teams.
  • Proficiency in synthesis, place and route (PnR), and sign-off convergence, including Static Timing Analysis (STA) and sign-off optimizations.

Job Requirements

  • Expertise in meeting demanding Power, Performance, and Area (PPA) requirements for complex subsystems/System on Chips (SoCs), place and route, and IP integration.
  • Experience in low power design implementation, including Unified Power Format (UPF), multi-voltage domains, and power gating.
  • Familiarity with ASIC design flows and physical design methodologies.
  • Strong understanding of circuit design, device physics, and deep sub-micron technology.
  • Experience working on multiple technology nodes in advanced processes.
  • Proficiency in automation to drive improvements in PPA.
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