SYSynopsys
Senior Design Verification Engineers
Bangalore ₹10-14 LPA Posted 30 May 2025
FULL TIME
System Verilog
Uvm
BSEE
MSEE
RTL Coding
+2 more
Job Description
What You ll Need:
- MSEE or BSEE with 10+ years of digital design and verification experience.
- Strong understanding of verification methodologies like System Verilog and UVM.
- Familiarity with RTL coding and design principles.
- Proficiency in scripting languages like Perl and Python for automation.
- Excellent debugging and troubleshooting abilities.
- Experience with test chip and full chip knowledge is an advantage.
- Proven leadership and team-building skills.
