Senior Design Engineer, Silicon

Responsibilities

• Define microarchitecture details such as interface protocol, block diagram, data flow, pipelines, etc.
• Perform Register-Transfer Level (RTL) development (SystemVerilog), RTL integration (Perl), debug functional/performance simulations.
• Perform RTL quality checks including Lint, CDC, RDC, Synthesis, Unified Power Format (UPF) checks.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience.
• 3 years of experience with Register-Transfer Level (RTL) design using Verilog/System Verilog and microarchitecture.
• Experience in handling low power schemes, power roll up and power estimations.
• Experience in Register-Transfer Level (RTL) quality sign-off flows (e.g., CDC, RDC, Lint, Power Intent or LEC).
• Experience with Perl or Python.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science.
• Experience with methodologies for low power estimation, timing closure, and synthesis.
• Experience with computer architecture.