SY

Senior Analog Design Engineer

Synopsys
Bangalore3-7 LPA Posted 30 May 2025
FULL TIME
Esd
ASIC ASIC design
CMOS
Ddr

Job Description

What You ll Need:

  • BTech/MTech in Electrical Engineering or related field.
  • Minimum of 3 years of experience with MTech or 5 years with BTech in CMOS circuit design and layout methodology.
  • Strong knowledge of deep submicron process technologies and CMOS processes.
  • Familiarity with JEDEC requirements for DDR interfaces and standards.
  • Experience with ASIC design flow and ESD concepts is an advantage.

Join WhatsApp Channel