RTL Design (Sr Eng/Lead/Staff/Sr Staff)

General Summary:

• 3 to 15 years of experience in ASIC/SoC design.
• Strong expertise in logic design, micro-architecture, and RTL coding (Verilog/SystemVerilog mandatory).
• Hands-on experience with SoC design and integration for complex SoCs.
• Knowledge of AMBA protocols: AXI, AHB, APB.
• Familiarity with SoC clocking, reset, debug architecture, and peripherals like USB, PCIe, SDCC.
• Understanding of memory controller designs and microprocessors is a plus.
• Collaborate closely with SoC verification and validation teams for pre- and post-silicon debug.
• Experience in low-power SoC design required.
• Proficient with multi-clock designs and asynchronous interfaces.
• Experience using ASIC development tools: Lint, CDC, Design Compiler, PrimeTime.
• Knowledge of constraint development and timing closure is a plus.
• Experience in synthesis and timing concepts is advantageous.
• Experience with padring creation and chip-level floorplanning is a plus.
• Excellent oral and written communication skills.
• Proactive, creative, curious, motivated to learn, and strong collaborator.

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or related field + 4+ years relevant experience.
• OR
• Master's degree in related fields + 3+ years relevant experience.
• OR
• PhD in related fields + 2+ years relevant experience.