RTL Design and Signoff -Staff Engineer

You have a keen eye for detail and can identify design/architecture pitfalls across clock/reset domain crossings.

Your ability to synthesize designs and ensure RTL and gate equivalence through formality checks is unmatched.

You are a collaborative team player, ready to integrate IPs in SoCs/Subsystems and create RTL designs that meet customer needs.

If you are ready to leverage your expertise in a role that shapes the future of semiconductor design, Synopsys is the place for you.

What You'll Be Doing:

• Perform RTL Quality Signoff Checks such as LINT, CDC, and RDC.
• Understand design/architecture and develop timing constraints for synthesis and timing.
• Run preliminary synthesis to ensure design can be synthesized as intended.
• Run formality to ensure equivalence of RTL and gates.
• Integrate IPs in SoCs/Subsystems and create RTL design as per customer needs.
• Collaborate with cross-functional teams to deliver high-quality RTL designs.

The Impact You Will Have:

• Ensure high-quality RTL Signoff for semiconductor designs.
• Contribute to the development of cutting-edge semiconductor technologies.
• Improve design efficiency and performance through effective timing constraints.
• Enhance the reliability and functionality of SoCs and subsystems.
• Support customer success by delivering tailored RTL designs.
• Drive innovation in RTL Design and Verification methodologies.