R&D Engineering,senior

• Generate test benches and test cases.
• Perform RTL and gate-level SDF-annotated simulations and debug.
• May perform mixed-signal (digital + analog) simulations and debug.
• Interact with our application engineers and provide guidance to customers.
• Participate in the generation of data books, application notes, and white papers.
• Perform physical verification and design rule checks to ensure design integrity and manufacturability.
• Understand tools like VC Spyglass, Verdi, & views like SDF, Liberty, etc., and other frontend views.
• Write RTL Code, with solid Verilog, PERL, and Python skills, and TCL is a good addition.
• Understand static timing analysis and synthesis, DFT/ATPG skills would be a plus.
• Knowledge of any high-speed communication protocol is not mandatory but an asset.
• Previous knowledge in customer support and/or silicon bring-up is a plus.

The Impact You Will Have:

• Strengthen and develop forecasting capabilities based on improved monitoring capacity.
• Ensure high-quality and reliable silicon lifecycle monitoring solutions.
• Enhance quality assurance methodology by adding more quality checks/gatings.
• Support internal tools development and automation to improve productivity across ASIC design cycles.
• Work with design engineers on new tools/technology and new features evaluation and adoption.
• Contribute to the successful and smooth operation of the engineering teams.

What You'll Need:

• Bachelor's or master's degree in electrical engineering or a related field.
• 3 to 7+ years of experience in A&MS frontend and backend views & collaterals development flows.
• Proficiency in industry-standard EDA tools, such as Cadence Virtuoso or Synopsys Custom Compiler.
• Exceptional knowledge of layout design methods, techniques, and methodologies.
• Experience with physical verification tools, such as Calibre or Assura.
• Understanding of semiconductor process technologies and their impact on layout design.