QU

Principal/Manager Physical Design CAD Engineer

Qualcomm
Noida4-11 LPA Posted 26 May 2025
FULL TIME
power optimization
Timing Closure

Job Description

  • Bachelors degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience.
  • OR
  • Masters degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience.
  • OR
  • PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.

Job Role

  • Work with Physical design engineers to rollout robust, identify areas for flow improvement methodologies.
  • (area / power / performance / convergence) , develop plans and
  • deploy/support them
  • Power performance area improvement using synthesis and place and route tools.
  • Support physical design flows using icc2/innovus tools
  • Provide tool support and issue debugging services to physical design
  • team engineers across various sites
  • Develop and maintain 3rd party tool integration and productivity
  • enhancement routines
  • Understand advance tech PNR and STA concents and methodologies and work closely with EDA vendors to deploy solutions.

Skill Set

  • Good TCL, Perl programming skills
  • Knowledge of one of Encounter/Innovus or Icc2 or Olympus tool (or
  • other equivalent PNR tool) is mandatory
  • Basic understanding of Timing/Formal verification/Physical
  • verification/extraction are desired
  • Ability to ramp-up in new areas, be a good team player and excellent
  • communication skills desired

Experience

15+ years of experience with the Place-and-route and timing closer and power analysis environment is required

Niche Skills

  • Handling support tools like Encounter / Innovus / edi / Icc2 / Olympus / Nitro (or other equivalent PNR tool). One or more of the above is mandatory*
  • Technology enablement for sub-5nm nodes from primary process nodes.
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