Principal Software Engineer ( Verification )

Key Responsibilities

• Design and develop Verification IP (VIP) using C/C++ and SystemVerilog/UVM.
• Manage and maintain multiple VIP components.
• Interact with customers to understand requirements and support VIP usage.
• Contribute to protocol and formal verification methodology development.
• Debug complex verification issues across IP and system-level environments.
• Lead or mentor a small team of engineers.
• Ensure high-quality VIP delivery aligned with Cadence standards.