SY

Principal R&D Engineer (Synthesis)

Synopsys
Noida14-19 LPA Posted 30 May 2025
FULL TIME
Hdl
C++
Verilog
Analog Design
Linux
+2 more

Job Description

  • Ability to develop new software architecture and good leadership skills.
  • Strong hands-on experience in C/C++ based software development.
  • Strong background in Design Patterns, Data Structure, Algorithms, and programming concepts.
  • Familiarity with multi-threaded and distributed code development.
  • Familiarity with ASIC design flow and the EDA tools and methodologies used therein.
  • Good knowledge of Verilog, SystemVerilog & VHDL HDL
  • Well versed with Software Engineering and development processes
  • Experience of production code development on Unix/Linux platforms.
  • Exposure to developer tools such as gdb, Valgrind
  • Exposure with source code control tool like Perforce.
  • Good analysis and problem-solving skills.

Desirable Skills:

  • Work experience in Synthesis tools
  • Work experience in EDA
  • Experience in technically leading significant size projects

Personal Attributes:

  • Highly enthusiastic and energetic team player with the ability to go an extra mile.
  • Good written and verbal communication skills.
  • Strong desires to learn and explore new technologies.

Join WhatsApp Channel