Principal Product Validation Engineer

Key Responsibilities

• Develop and maintain functional verification environments for complex digital systems and SoC designs.
• Perform simulation and emulation-based verification using Verilog and/or VHDL.
• Create and execute testbenches using SystemVerilog and UVM methodologies.
• Implement constrained random verification, coverage-driven verification, and regression testing strategies.
• Debug functional issues using Cadence and other industry-standard EDA tools.
• Analyze verification results and perform root-cause analysis of failures.
• Develop automation scripts to improve verification efficiency and reduce manual effort.
• Collaborate with RTL design, architecture, and validation teams to ensure design correctness.
• Contribute to verification planning, test strategy development, and coverage closure.
• Support SoC-level verification for multi-block and complex subsystem integration.