Principal Design Engineer

Key Responsibilities

• Define long-term DV architecture and scalable verification strategy for CPU/DSP and configurable processor IPs.
• Architect and develop reusable verification infrastructure using SystemVerilog, UVM, and C/C++.
• Build and enhance simulation testbenches combining RTL and C/C++-based architectural models.
• Drive adoption of advanced verification methodologies including formal verification and AI-driven coverage analysis.
• Ensure coverage-driven verification completeness for ISA, pipeline, memory subsystem, and processor integration scenarios.
• Collaborate closely with microarchitecture, RTL, and software teams to align verification plans with ISA requirements.
• Establish metric-driven verification (MDV) practices and ensure quality standards across global teams.
• Mentor and guide senior and junior verification engineers across multiple geographies.
• Review and approve verification strategy, architecture, and execution plans.
• Continuously improve verification scalability for multiple processor configurations and product generations.