SY

Principal Applications Engineer STA

Synopsys
Bangalore5-7 LPA Posted 30 May 2025
FULL TIME
Tcl
Eda
System Verilog
RTL
SDC
+2 more

Job Description

What You ll Need:

  • Proficiency with STA, SDC.
  • Proficiency with RTL, System Verilog.
  • Strong understanding of front-end EDA design methodologies.
  • Strong Perl, Tcl, or Python scripting skills.
  • Prior experience with logic synthesis tools.
  • Prior experience using or supporting SDC tools (a significant plus).
  • Prior experience with RTL simulation and SVA (a plus).
  • Sound communication skills, both verbal and written.
  • Ability to produce detailed product requirement documents.
  • BS in Electrical or Computer Engineering with 10+ years of experience in STA/Synthesis/Front-End Flows.

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