Physical Design Methodology Engineer

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
• OR
• Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
• OR
• PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
• QCT is actively seeking candidates for VLSI Methodology and R&D positions. You will be part of the backend methodology team that develops innovative solutions for Qualcomms chip implementation flow.
• As a digital ASIC R&D Engineer, you will play a vital role in addressing challenges with Performance, Power, and Area (PPA) scaling tradeoffs to qualify technology entitlement of advance process nodes. You will be responsible for research and develop methods to improve efficiency of digital ASIC design flow and chip quality/yield. The job scope includes design automation, post-silicon debug and data mining.

Required Skills

• Coding with Python, Perl, TCL and/or C++
• Working knowledge in Digital VLSI implementation (netlist to GDS) STA Power Distribution Network (PDN)
• Hands on experience with EDA tools (Primetime, ICC2, Innovus, Tempus, etc.)

Expected Experience: 2- 10 years of relevant industry experience