MTS Software Development Eng.

THE ROLE: 

Performance modelling and evaluation of ACAP workloads to eliminate bottlenecks as early as possible and guide the architecture of future generation devices. This is a challenging role in the FPGA Silicon Architecture Group in AECG business unit of AMD in Hyderabad. 

ABOUT THE TEAM:

AECG group in AMD designs cutting edge FPGAs and Adaptable SOCs consisting of processor subsystems and associated peripherals, programmable fabric, memory controllers, I/O interfaces and interconnect.  

KEY RESPONSIBILITIES: 

• Modelling and simulation of workload dataflow networks and clock accurate SOC components.
• Performance analysis and identification of bottlenecks
• Quick prototyping, long-term design decisions, and exploring novel architectures
• Enhancement of the existing tools and knowledgebase
• Collaborating with architects in the development of next generation devices
• Collaborating with customer facing teams to identify scope of optimization for future market scenarios
• Breaking down system level designs into simpler dataflow models and identify bottlenecks, capture memory and communication overheads
• Knowledge sharing with teammates through thorough documentation

PREFERRED EXPERIENCE: 

• Preferred experience in SOC architecture OR Performance analysis.
• Experienced in modelling and simulation
• Experience in developing clock accurate models and analytical models of dataflows.
• Strong background in Computer architecture, Hardware performance metrics and bottlenecks.
• Experience in performance profiling, creating experiments to address various use-cases and doing design space exploration.
• Good to have experience of creation of designs for ACAP devices or HLS.
• Good communication skills

ACADEMIC CREDENTIALS: 

• B.Tech/M.Tech/PhD in Electrical/Computer Engineering, Computer Science or related fields, with appropriate prior experience