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MTS Silicon Design Engineer

Advanced Micro Devices (AMD)
Bangalore8-13 LPA Posted 22 May 2025
FULL TIME
Simulation
Gaming
Apache
Physical Design
Timing Closure
+2 more

Job Description

  • Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
  • Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
  • Work with IP SOC teams across all our sites (GFX, Memory controller, Multimedia engines, IOs, PCIE ) to understand the features and create verification plans
  • Will help scoping out the testbench architecture and the simulation configuration, test planning, coverage planning etc
  • Will develop system config and initialization sequences to various system configurations at the SOC
  • Will work with Graphics/IO IP team and verify some of the graphics features at GPU SOC level, give out callouts to IPs and verify the SOC context.
  • Will work on creating test bench components like checkers, monitors, test cases, coverage infrastructure, running simulations, debug, coverage analysis closure etc
  • Estimate the time required to write the new feature tests and any required changes to the test environment
  • Build the directed and random verification tests
  • Debug test failures to determine the root cause; work with RTL and IP engineers to resolve design defects and correct any test issues
  • Review functional and code coverage metrics modify or add tests or constrain random tests to meet the coverage requirements

PREFERRED EXPERIENCE:

  • B.E/B.Tech/M.E/M.Tech in Electrical/Electronic Engineering
  • 8+ years experience in Design Verification preferably with SOCs.
  • Experience with SOC verification that involves Graphics core, memory subsystem, PCIE subsystems, cache coherency, interconnects would be a plus.
  • Experience with setting up verification infrastructure would be desirable.
  • Should have strong experience with SV/UVM Methodology
  • Must have excellent knowledge of Design verification flows
  • Experience in developing complex test bench/model in Verilog, System Verilog or SystemC
  • Experience in writing test plans and test cases
  • Excellent hands-on debug skills
  • Strong Verilog, System Verilog, PLI/DPI interface, SystemC or C/C++, Perl/shell script programming skills.
  • Must have good communication skills and the ability and desire to foster a team environment.
  • Must be we'll organized and should be good at multi-tasking.
  • Good understanding for digital system and computer organization
  • Should be a confident coder and be comfortable debugging general hardware/software problems.
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