MTS Silicon Design Engineer

Engineer with good attitude who seeks new challenges and has good analytical and and problem-solving skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones.

KEY RESPONSIBILITIES:

• Working on static timing analysis setup and signoff of multi-corner multi-voltage designs.
• Owning timing execution to meet timing requirements including timing budgeting, repeater planning, constraints/exceptions generation and management
• Areas of focus include Timing analysis and verification, extraction and noise glitch analysis
• Engaging closely with Design teams to understand the design and convergence challenges and providing ECOs with a focus on PPA and TAT optimizations.
• Hierarchical timing analysis and convergence at block, section and fullchip level.
• Understanding CTS strategies, LVF/POCV variations and providing feedback to the implementation/methodology teams.
• Handling different PNR tools - Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk

PREFERRED EXPERIENCE:

• 8+ years of professional experience in physical design, preferably with high performance designs.
• Demonstrated ability in areas of Timing analysis, timing convergence, SI/Noise analysis, Signoff quality (PVT, process variation effects, guardbanding, etc), Timing ECOs, PV/Noise modelling, .libs, is a must.
• Multi-voltage scenarios design handling knowledge is expected. STA closure/convergence execution on Low power designs is an added advantage.
• Expertise in industry standard EDA tools (Primetime) and ASIC design flow is required
• Hands-on experience with Physical Design implementation is a plus
• Proficiency in scripting language, such as, Perl and Tcl.
• Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications.
• Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction.
• Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams
• Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm
• Excellent physical design and timing background.
• Good understanding of computer organization/architecture is preferred.
• Strong analytical/problem solving skills and pronounced attention to details.