Logic Design Engineer

Overview

At IBM Infrastructure & Technology, we are at the forefront of designing and managing the systems that sustain global operations. Our focus spans high-resiliency mainframes, hybrid cloud platforms, networking, automation, and site reliability. Our teams are dedicated to ensuring the performance, security, and scalability that clients and industries rely on daily. A career in Infrastructure & Technology offers the opportunity to address complex challenges through curiosity and teamwork. You'll engage with a variety of technologies and collaborate with colleagues globally to deliver robust, future-ready solutions that drive innovation. With a strong emphasis on continuous learning, career advancement, and a supportive environment, IBM provides the resources necessary to develop expertise and influence the infrastructure that propels progress.

Your Responsibilities

• Partner with micro architects and designers to implement CPU micro architectural features aimed at resolving PPA challenges for designated workloads.
• Work alongside the Silicon Bringup team and Software team to validate and troubleshoot microarchitecture and its performance.
• Exhibit strong communication skills and a proactive approach to finalize micro architectural proposals within the Core and Cache team, engaging with technical stakeholders throughout the Chip/System via presentations and documentation.
• Demonstrate excellent collaborative and interpersonal skills, along with a proven ability to mentor new design team members.
  
  

Preferred Education

Master's Degree

Essential Technical and Professional Qualifications

• 5-10 years of experience in high-performance microprocessor architecture, micro architecture, and computer architecture.
• In-depth understanding of Processor Instruction Set Architecture (e.g., ARM, X86, Power).
• Comprehensive knowledge and experience in CPU microarchitecture and architecture encompassing Fetch, Decode, Load-Store, L1 and L2 caches, Prefetch, and Coherency.
• Additional expertise in Memory Design, Memory Ordering Rules, Load-Store, Pipeline optimization, and PPA optimization is preferred.
• Proficient in RTL design with hands-on experience in Processor/ASIC design flow, including design, verification, PD synthesis, ECO, and bring-up.
  
  

Preferred Technical and Professional Experience

• Advanced Static Timing: A thorough understanding of static timing and its relevance in chip logic development can be beneficial in achieving business objectives.
• Front-end Processing Knowledge: Familiarity with front-end processing and its significance in chip logic development can play a crucial role in the evolution of cognitive systems logic design.
• Post-Si Debug Experience: Experience with Post-Si debugging is desirable.
• Performance & Power Analysis: Knowledge of analyzing Performance & Power Tools data and devising features to address PPA challenges is advantageous.