CA

Lead Verification Engineer

Cadence
Noida5-10 LPA Posted 5 Jun 2026
FULL TIME
Machine Learning
System Design
Simulation
Uvm
Semiconductor
+4 more

Job Description

Key Responsibilities

  • Apply machine learning techniques to enhance and optimize pre-silicon functional verification workflows such as formal verification and UVM-based verification
  • Develop and contribute to agentic AI systems using large language models and modern ML frameworks to accelerate verification processes
  • Leverage AI-enhanced EDA tools to improve efficiency across design and verification cycles
  • Work closely with customers to understand verification requirements and translate them into effective technical solutions
  • Collaborate with ML and software engineering teams to ensure correctness, performance, and reliability of developed solutions
  • Debug complex pre-silicon verification failures using waveform analysis and simulation tools
  • Stay updated with advancements in AI, ML, and hardware verification technologies and contribute to internal knowledge sharing

Join WhatsApp Channel