CACadence
Lead Verification Engineer
Bangalore ₹5-9 LPA Posted 4 Jun 2026
FULL TIME
Ovm
Verilog
Uvm
Asic verification
formal verification
+3 more
Job Description
Key Responsibilities
- Apply machine learning techniques to optimize and automate traditional pre-silicon functional verification methodologies such as Formal Verification and UVM-based verification
- Develop AI-driven and agentic verification solutions using LLMs and advanced ML technologies to improve verification productivity and coverage
- Leverage AI-enhanced Electronic Design Automation (EDA) tools to accelerate semiconductor design and verification workflows
- Design, implement, and validate innovative verification methodologies that improve efficiency, quality, and scalability
- Perform pre-silicon verification using simulation, formal verification, and coverage-driven methodologies
- Debug complex verification failures using waveform viewers, simulation tools, and root-cause analysis techniques
- Collaborate closely with machine learning engineers, software engineers, and verification teams to ensure solution correctness and effectiveness
- Engage directly with customers to understand verification challenges and deliver practical AI-enabled solutions
- Evaluate and integrate emerging AI technologies into verification workflows and methodologies
