CA

Lead Software Engineer

Cadence
Noida5-9 LPA Posted 5 Jun 2026
FULL TIME
C++
Verilog
Simulation
Uvm
Cadence Tools
+6 more

Job Description

Key Responsibilities

  • Develop and maintain functional verification environments for complex digital and SoC designs.
  • Perform simulation and emulation-based verification using industry-standard Hardware Description Languages (HDLs) and Hardware Verification Languages (HVLs).
  • Debug design and verification issues using Cadence and other EDA tools.
  • Design, implement, and enhance reusable verification components and testbench architectures.
  • Develop automation solutions using scripting languages to improve verification productivity and workflow efficiency.
  • Collaborate with design, verification, application engineering, and customer teams to resolve technical challenges.
  • Analyze verification results, identify root causes of failures, and implement corrective solutions.
  • Support customer engagements by providing technical expertise related to verification methodologies and EDA tools.
  • Contribute to verification planning, test development, coverage analysis, and verification closure activities.
  • Drive continuous improvement in verification processes, methodologies, and tool usage.

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