CA

Lead Software Engineer

Cadence
Noida5-9 LPA Posted 4 Jun 2026
FULL TIME
Hdl
Algorithms
systemverilog
Data Structures

Job Description

Key Responsibilities

  • Design, develop, and maintain scalable and maintainable C/C++ code for HDL compiler and runtime systems
  • Build and enhance HDL compiler front-end components, especially for SystemVerilog (SV)
  • Improve compiler performance, infrastructure efficiency, and toolchain reliability
  • Work on simulation and synthesis-related flows for RTL design environments
  • Collaborate with cross-functional and cross-geography teams to deliver robust EDA solutions
  • Analyze complex software problems and provide optimized, production-quality solutions
  • Ensure code quality through design reviews, testing, and performance optimization
  • Contribute to system design and architecture decisions for compiler and runtime frameworks
  • Continuously learn and adopt new technologies relevant to EDA and compiler development

Join WhatsApp Channel