Lead Product Validation Engineer

Key Responsibilities

• Design, develop, and maintain functional verification environments for complex digital systems and SoC designs.
• Perform verification using Verilog and/or VHDL in simulation and emulation flows.
• Develop testbenches and verification components using SystemVerilog and UVM.
• Execute constrained-random verification, regression testing, and coverage-driven verification.
• Debug functional and system-level issues using Cadence and other EDA tools.
• Perform root-cause analysis of design and verification failures.
• Develop automation scripts to improve verification efficiency and reduce manual effort.
• Collaborate with RTL design, architecture, and validation teams to ensure design correctness.
• Contribute to verification planning, test strategy development, and coverage closure activities.
• Support SoC-level verification for complex multi-block and subsystem integration.