Lead Product Validation Engineer

Key Responsibilities

• Develop and execute functional verification plans for complex digital and SoC designs.
• Design, implement, and maintain reusable verification environments using SystemVerilog and UVM.
• Perform simulation and emulation-based verification of semiconductor designs.
• Debug design and verification issues using Cadence and other industry-standard EDA tools.
• Develop verification testbenches, checkers, assertions, and coverage models.
• Analyze verification results and perform root-cause analysis of failures.
• Contribute to verification closure activities including functional, code, and assertion coverage.
• Develop automation scripts to improve verification productivity and workflow efficiency.
• Collaborate with RTL, architecture, validation, and software teams to ensure design quality.
• Support product validation and verification signoff activities.