CACadence
Lead Product Engineer
Noida ₹5-9 LPA Posted 4 Jun 2026
FULL TIME
Eco
Verilog
Physical Design
Signal Integrity
Timing Constraints
Job Description
Key Responsibilities
- Validate, improve, and regression test the Tempus Signoff ECO solution to ensure high product quality and reliability
- Collaborate with R&D teams, senior product engineers, and release teams to define product specifications and enhancements
- Develop and optimize product flows to improve timing closure efficiency, quality, and performance
- Define test methodologies and create automated validation frameworks for product verification
- Work closely with customers and internal teams to address complex timing signoff and ECO challenges
- Analyze and debug timing, signal integrity, and implementation issues in advanced semiconductor designs
- Support timing and power closure activities using automated and manual ECO methodologies
- Develop automation scripts to improve productivity and streamline validation workflows
- Participate in product qualification, regression testing, and release readiness activities
- Contribute to continuous improvement of product quality, performance, and customer satisfaction
