Lead Formal Verification Engineer

What You ll Need:

• Bachelor s or Master s degree in Electrical Engineering, Computer Engineering, or a related field. Advanced degrees preferred.
• 2 - 6 years of experience in formal verification of digital design IPs, with a strong track record in verifying complex IPs.
• Deep understanding of formal verification methodologies, including property-based and equivalence checking, SystemVerilog Assertions (SVA), and protocol compliance.
• Strong familiarity with industry-standard formal verification tools, such as Cadence JasperGold, Synopsys VC Formal, or Mentor Questa Formal.
• Extensive experience in digital design and verification for high-speed interconnect protocols.