Lead Design Engineer

Key Responsibilities

• Develop and execute verification plans for IP, subsystem, and SoC-level designs.
• Create detailed test plans and functional coverage strategies to ensure design completeness.
• Develop and close functional coverage, code coverage, and assertions for complex ASIC designs.
• Perform design verification using SystemVerilog/UVM or equivalent HVL methodologies.
• Work on post-silicon validation and bring-up activities to ensure silicon readiness.
• Debug complex verification and design issues across IP and system levels.
• Collaborate with cross-functional teams to ensure verification quality and schedule adherence.
• Apply scripting and automation techniques to improve verification efficiency.
• Ensure compliance with verification processes and best practices.
• Contribute to continuous improvement of verification methodology and flows.