Lead Design Engineer

Key Responsibilities:

• Proficient in Verilog coding and RTL design, including data path designs.
• Conduct RTL checks such as LINT, SDC, and CDC.
• Familiar with synthesis flow and timing constraints.
• Write Verilog testbenches and run simulations.
• Work with interface protocols such as UCIe, PCIe, USB, MIPI (DPHY), HDMI/Display.