Lead Application Engineer

Responsibilities:

• Provide expertise in analog IC layout design and ensure adherence to foundry process and design rules.
• Work extensively with Cadence Virtuoso for analog/custom IC physical design workflows.
• Understand and apply advanced node design rules and Virtuoso techfile constraints.
• Develop and use scripting solutions to automate layout and design tasks.
• Handle complete analog back-end flow including floorplanning, block-level layout, physical verification, extraction, EM/IR analysis, and signoff.
• Support chip integration and ensure robust design closure using Cadence tools.