GOGoogle Inc
Formal Verification Engineer, Silicon, Google Cloud
Bangalore ₹3-8 LPA Posted 25 Apr 2025
FULL TIME
Uvm
systemverilog
Job Description
Role Responsibilities:
- Plan and develop formal verification strategies for complex digital design blocks.
- Create properties and constraints using formal verification tools for property verification.
- Resolve verification challenges and improve methodologies for better results.
- Architect and implement reusable components to enhance formal verification processes.
Job Requirements:
- Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
- 3 years of experience with verification methodologies and languages such as UVM and System Verilog.
- Experience with designing and maintaining verification test benches and environments.
