DFT Engineer / Sr Engineer

• Interfac e with design team to ensure DFT design rules and coverages are met.
• Generating high quality manufacturing ATPG test patterns for stuck-at (SAF) , transition fault (TDF ) models through the use of on-chip test compression techniques.
• M BIST verification (including repair), test pattern generation through Mentor tool.
• ATPG (SAF, TDF) and MBI ST verification using unit delay and min/max timing corner s imulations .
• Work with the P roduct /Test engineering teams on the delivery of manufacturi ng test patterns for ATE .
• Responsible for supporting post silicon debug effort, issue resolution .
• Responsible for Diagnostic Tool generation for ATPG , MBIST and bring-up on ATE.
• Developing, enhancing and maintaining scripts as necessary

Minimum Qualifications:

• Bachelors degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
• OR
• Masters degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
• OR
• PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.Minimum of 1-6 year s experience in ASIC/DFT - simulation and Silicon validation
• Detailed knowledge on DFT concepts, pattern simulation, Silicon debug and yield enhancement
• In depth knowledge and hands-on experience in ATPG - coverage analysis.
• In depth knowledge of Memory verification, repair and failure root-cause analysis.
• Experience with any of these tools is required
• ATPG - TestKompress
• MBIST - Mentor ETVerify
• Simulation - VCS (preferred), modelsim .
• Expertise in scripting languages such as Perl , shell, etc is an added advantage
• Ability to work in an international team, dynamic environment with good communication skills
• Ability to learn and adapt to new tools , methodologies.
• Ability to do multi-tasking & work on several high priority designs in parallel